a) Field of the Invention
The present invention relates to a wiring pattern forming method, and more particularly to a wiring pattern forming method suitable for manufacture of highly integrated semiconductor devices.
b) Description of the Related Art
Wiring patterns of a semiconductor integrated circuit or the like are formed in the following method. A conductive layer is formed on the surface of an underlying layer, a resist pattern having a desired wiring layout is formed on the conductive layer through photolithography. By using the resist pattern as an etching mask, the conductive layer is etched to form wiring patterns.
If side etching (under cut) occurs during the etching process of the conductive layer, the pattern of the conductive layer becomes different from the resist pattern so that a size precision of the final conductive pattern lowers. From this reason, anisotropic etching hard to form side etching is widely used. As anisotropic etching, reactive ion etching (RIE), magnetron RIE, and the like have been used. RIE uses etching gas which generates ions which react with metal components of a conductive layer, and remove the conductive layer.
In RIE, a voltage is applied between parallel plate electrodes, and plasma of introduced gas is generated through capacitive coupling. In magnetron RIE, a magnet is placed under a substrate to control the trajectory of ions.
In order to realize a higher integration, it is desired to form wiring patterns having a higher density. In forming wiring patterns having a higher density, it is necessary to improve a size precision of etching. In order to improve productivity, it is also desired to speed up an etching rate.
In order to speed up an etching rate, it is desired to form high density plasma. In order to improve a size precision, it is desired to lower a pressure in an etching chamber and reduce the number of collisions among molecules (ions).
To satisfy such needs, etching techniques utilizing low pressure, high density plasma have been developed. For example, if inductive coupling is used in place of capacitive coupling, plasma having a lower pressure and a higher density can be generated.
However, etching using such low pressure, high density plasma is associated with a new problem to be solved. Namely, microloading effects become conspicuous when etching using such low pressure, high density plasma is performed. The microloading effect provides a slower etching rate in a narrower etching space area than that in a broader etching space area.
If the microloading effect is large, the amounts of positive and negative charges injected into a conductive layer to be etched are not equal, and the amount of incoming positive charges becomes excessive. Depending upon the amount of accumulated charges, some charges may tunnel through a gate insulating film or the like of a MOS transistor, and the life time of the gate insulating film is shortened, depending on the accumulated amount of the tunnel current. This phenomenon is called electron shading damage which is considered to be ascribed to shading of electrons which are to be otherwise implanted via the resist pattern into a substrate surface layer. Electron shading damage is caused when the microloading effect exists and the temperature of electrons in plasma is high. If the density of high energy electrons is high, the electron shading damage becomes large.
In addition to electron shading damage, there is a phenomenon of forming notches in the lower portion of an etched conductive layer.
The reason of why electron shading damage and notches are hard to be formed in RIE heretofore performed may be ascribed to a low temperature of electrons. Even if the temperature of electrons is high, it can be expected that the electron shading damage is hard to occur, if the microloading effect does not exist. From these viewpoints, there are needs of lowering an electron temperature, lowering a density of high energy electrons, or eliminating the microloading effects.
The electron shading damage is considered to be caused by the upper side wall of an insulating mask charged with electrons. Therefore, a method has been proposed by which a conductive layer is etched by using a conductive mask which is not charged with electrons.
With this method, a three-layer structure is used. Specifically, a conductive polymer layer is coated on a conductive layer to be etched, and an inorganic mask layer is formed on the conductive polymer layer, the inorganic mask layer being a glass layer formed through spin-on, an SiN layer or an SiO.sub.2 layer formed thorough sputtering, or the like. On this inorganic mask layer a resist mask pattern is formed through photolithography. First, the pattern of the resist mask is transferred to the inorganic mask layer. Then, by using the transferred pattern of the inorganic mask layer as a mask, the underlying conductive polymer layer is etched. The inorganic mask and resist mask over the conductive mask are usually removed. In this manner, the conductive mask is formed.
The number of these processes is larger than that of the processes using only a resist mask. The conductive polymer layer has a low etching selection ratio than that of an inorganic mask such as SiO.sub.2 and SiN so that a thickness similar to that of a resist layer is required when the conductive polymer layer is used as a mask. Therefore, an aspect ratio of a mask pattern becomes high and the microloading effect occurs. Since the microloading effect exists even if the conductive mask is used, it is not possible to reduce the amount of over-etching of a layer under the conductive layer.
Electron shading damage is generated during an over-etch, after the etching in a broader space area is finished and the conductive layer in a narrower space area is electrically separated from the semiconductor substrate. From this reason, a method has been proposed by which an over-etch is performed at a low plasma density which can lower the density of high energy electrons.
It has been reported that electron shading damage can be reduced even if an inductive coupling type plasma etcher is used, by lowering a supply power during an over-etch to lower the density of high energy electrons. However, a low plasma density during an over-etch lowers the etching rate and productivity.
In another approach to reducing electron shading damage, it is proposed to use pulse modulation plasma. By pulsating a supply power, an average power can be lowered and the electron temperature can be lowered. However, a specific apparatus is required to generate pulsated plasma.
Japanese Patent Laid-open Publication No. HEI-4-350932 proposes a method of etching a polycide electrode formed on a semiconductor substrate in two steps. The polycide electrode is a lamination of a lower polysilicon layer and an upper tungsten silicide layer.
As an etching gas of the upper tungsten silicide layer, a mixture gas of a gas selected from a group consisting of Cl.sub.2, Br.sub.2, HCl, and HBr and a gas selected from a group consisting of SF.sub.6, NF.sub.3, and F.sub.2 is used. As an etching gas of the lower polysilicon layer, a gas selected from a group consisting of Cl.sub.2, Br.sub.2, HCl, and HBr or a mixture gas of the above-mentioned gas and a gas not containing F such as an inert gas. It is reported that this etching method suppresses side etching and improves an etching selection ratio.
Japanese Patent Laid-open Publication No. HEI-7-74156 proposes a method of plasma-etching aluminum by using a mixture gas of a chlorine-containing gas and a boron-containing gas, added with 20% or less of nitrogen gas or flon gas (CF.sub.4, CHF.sub.3, C.sub.2 F.sub.6). By adding the nitrogen gas or flon gas, the microloading effects are suppressed, and by setting the addition amount of the nitrogen gas or flon gas to 20% or less, the etching selection ratio is maintained good.
U.S. Pat. No. 5,219,485 discloses a method of etching a silicide layer of a polycide electrode by adding 20 vol. % or less of at least one of a boron-containing gas and an oxygen gas to a mixture gas of Cl.sub.2, BCl.sub.3 and HCl. It is reported that this etching method can improve a pattern size precision and maintain a high etching selection ratio relative to an oxide film.
If low pressure, high density plasma is used in order to improve an etching rate, electron shading damage is generated.